Leakage Power Reduction Using Bitwidth Optimization

Leakage power dissipation constitutes an increasing fraction of the total power in modern semiconductor technologies. Designing power efficient products will require consideration of leakage power in the earliest phases of design. This paper addresses bitwidth optimization focusing on leakage power reduction for system-level low-power design. By means of tuning the design parameter, bitwidth tailored to a given application requirements, the datapath width of processors and size of memories are optimized resulting in significant leakage power reduction besides dynamic power reduction. In our experiments for several real embedded applications, power reduction without performance penalty are reported range from about 21.5% to 66.2% of leakage power, and 14.5% to 59.2% of dynamic power.